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- 品牌NXP
- 数量300000
- 批号14
- 封装SOP
- 说明The HEF40106B provides six inverting buffers. Each input has a Schmitt trigger circuit. The inverting buffer switches at different points f positive-going negative-going signals. The difference between the positive voltage (VT+) the negative voltage (VT-) is defined as hysteresis voltage (VH).
The HEF40106B may be used f enhanced noise immunity to “square up” slowly changing wavefms.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, another input.
Features benefits
Schmitt trigger input discrimination
Fully static operation
5 V, 10 V, 15 V parametric ratings
Stardized symmetrical output acteristics
Operates across the automotive temperature range from -40 °C to +125 °C
Complies with JEDEC stard JESD 13-B
Applications
Wave pulse shapers
Astable multivibrats
Monostable multivibrats
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- 品牌NXP
- 数量300000
- 批号14
- 封装SOP
- 说明The HEF4011B is a quad 2-input N gate. The outputs are fully buffered f the highest noise immunity pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS(usually ground). Unused inputs must be connected to VDD, VSS, another input. The device is suitable f use over both the industrial (-40 °C to +85 °C) automotive (-40 °C to +125 °C) temperature ranges.
Features benefits
Fully static operation
5 V, 10 V, 15 V parametric ratings
Stardized symmetrical output acteristics
Operates across the automotive temperature range from -40 °C to +125 °C
Complies with JEDEC stard JESD 13-B
Inputs outputs are protected against electrostatic effects
Applications
Automotive industrial
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- 品牌NXP
- 数量300000
- 批号14
- 封装SOP
- 说明The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) outputs (Q, Q). Data is accepted when CP is LOW is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD SD inputs are independent override the D CP inputs. The outputs are buffered f best system perfmance. The clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS another input. The device is suitable f use over both the industrial (-40 °C to +85 °C) automotive (-40 °C to +125 °C) temperature ranges.
Features benefits
Tolerant of slow clock rise fall times
Fully static operation
5 V, 10 V, 15 V parametric ratings
Stardized symmetrical output acteristics
Operates across the automotive temperature range from -40 °C to +125 °C
Complies with JEDEC stard JESD 13-B
Applications
Automotive industrial
Counters dividers
Registers
Toggle flip-flops
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- 品牌NXP
- 数量300000
- 批号14
- 封装SOP
- 说明The HEF4069UB is a general purpose hex inverter. Each inverter has a single stage.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS(usually ground). Unused inputs must be connected to VDD, VSS, another input.
It is also suitable f use over both the industrial (-40 ℃ to +85 ℃) automotive (-40 ℃ to +125 ℃) temperature ranges.
Features benefits
Fully static operation
5 V, 10 V, 15 V parametric ratings
Stardized symmetrical output acteristics
Operates across the automotive temperature range from -40 ℃ to +125 ℃
Complies with JEDEC stard JESD 13-B
Applications
Automotive industrial
Oscillat
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- 品牌NXP
- 数量250000
- 批号14
- 封装SOP
- 说明The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC stard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC00; 74HCT00 provides a quad 2-input N function.
Features benefits
Input levels:
F 74HC00: CMOS level
F 74HCT00: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from –40 ℃ to +85 ℃ from –40 ℃ to +125 ℃
SeriesSO
Logic functions in small outline surface mount packages
SeriesHC(T)
High-speed CMOS HC(T)
Series74HC(T)00
Quad 2-input N gate
Parametric search all N gates
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- 品牌NXP
- 数量250000
- 批号14
- 封装SOP
- 说明The 74HC04; 74HCT04 is a hex inverter. The inputs include clamp diodes that enable the use of current limiting resists to interface inputs to voltages in excess of VCC.
Features benefits
Complies with JEDEC stard JESD7A
Complies with JEDEC stard JESD8-1A
Input levels:
F 74HC04: CMOS level
F 74HCT04: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C from -40 °C to +125 °C
SeriesSO
Logic functions in small outline surface mount packages
SeriesHC(T)
High-speed CMOS HC(T)
Series74HC(T)04
Hex inverter
Parametric search all Buffers/inverters/drivers
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- 品牌NXP
- 数量250000
- 批号14
- 封装SOP
- 说明The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device is pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1 A3) when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7).
The 74HC138; 74HCT138 features three enable inputs: two active LOW (E1 E2) one active HIGH (E3). Every output is HIGH unless E1 E2 are LOW E3 is HIGH.
This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs one inverter.
The 74HC138; 74HCT138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input the remaining enable inputs as strobes. Permanently tie unused enable inputs to their appropriate active HIGH- LOW-state.
The 74HC138; 74HCT138 is identical to the 74HC238; 74HCT238 but has inverting outputs.
Features benefits
Demultiplexing capability
Multiple input enable f easy expansion
Complies with JEDEC stard no. 7A
Ideal f memy chip decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM EIA/JESD22-A114-F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C from -40 °C to +125 °C
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- 品牌NXP
- 数量250000
- 批号14
- 封装SOP
- 说明The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA DSB either input can be used as an active HIGH enable f data entry through the other input. Data is shifted on the LOWtoHIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register fces all outputs LOW, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resists to interface inputs to voltages in excess of VCC.
Features benefits
Input levels:
F 74HC164: CMOS level
F 74HCT164: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC stard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 ℃ to +85 ℃ -40 ℃ to +125 ℃.
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- 品牌NXP
- 数量250000
- 批号14
- 封装SOP
- 说明The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with JEDEC stard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load serial-in shift registers with complementary serial outputs (Q7 Q7) available from the last stage. When the parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the register asynchronously.
When PL is HIGH, data enters the register serially at the DS input shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the succeeding stage.
The clock input is a gated- structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment f the CP CE inputs is arbitrary can be reversed f layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP HIGH f predictable operation. Either the CP the CE should be HIGH befe the LOW-to-HIGH transition of PL to prevent shifting the data when PL is activated.
Features benefits
Asynchronous 8-bit parallel load
Synchronous serial input
Complies with JEDEC stard no. 7A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C from -40 °C to +125 °C
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- 品牌NXP
- 数量250000
- 批号14
- 封装SOP
- 说明The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC stard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a stage register 3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the stage register on a positive-going transition of the stage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the stage register.
The shift register has a serial input (DS) a serial stard output (Q7S) f cading. It is also provided with asynchronous reset (active LOW) f all 8 shift register stages. The stage register has 8 parallel 3-state bus driver outputs. Data in the stage register appears at the output whenever the output enable input (OE) is LOW.
Features benefits
8-bit serial input
8-bit serial parallel output
Stage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 ℃ to +85 ℃ from -40 ℃ to +125 ℃